Evaluation of Multi-Cell Upsets at the 5-nm Bulk FinFET Technology Node
Yoni Xiong, Vanderbilt University
Electronic systems deployed for offensive and defensive purposes are exposed to ionizing radiation in space and terrestrial environments, which can result in malfunctions due to single-event (SE) effects. These electronic systems are routinely updated with the latest semiconductor technologies to achieve the highest performance and capabilities. Memories are a critical component of electronic systems and have become increasingly vulnerable to data corruption with scaling. Error-correcting codes have been effectively used for mitigating these effects when only a single data bit is upset in a word. With scaling, a single ionizing particle may corrupt multiple memory bits, resulting in multi-cell upsets (MCUs) or multi-bit upsets (MBUs) when the bits are in the same word. This work investigated MCUs and MBUs in single-port and two-port SRAMs and D-FF register circuits at a 5-nm bulk FinFET technology. Experimental results for MCU and MBU sizes and occurrence frequencies are presented for alpha particles and heavy-ions across a range of operating voltages. MCUs and MBU in both SRAM designs were observed at nominal supply voltage and alpha particle exposures, but none were observed in the D-FF register circuits. For reduced supply voltages and under high-LET particle exposures, MCUs accounted for the majority of events in the SRAMs and register circuits, with upset sizes as large as 9-bits and 5-bits, respectively. Technology Computer Aided Design (TCAD) simulations show that the sensitive area increases with supply voltage reductions and particle LET increases. The results of this study will help designers understand the extent of MCUs and MBUs at a 5-nm bulk FinFET node and inform critical SRAM and register design parameters, such as error-correction circuit complexity, interleaving distance, and layout for effective mitigation of SE effects.